A “carry generate gate” is a circuit that may be used as a building block for more complex logic circuits such as adders, 3-2 reducers, 4-2 reducers, and redundant-form adders. Carry generate circuits provide outputs, in accordance with known functionality, that are based upon data input bits. Multiple carry generate circuits may be used as building blocks in a more complex circuit, and different types of carry generate circuits may be used at different stages of the more complex logic circuit. Typically, different stages represent different bit positions of the input and/or output data. For example, a carry-look ahead adder may include a first stage carry generate gate, which may provide the first bit of a carry look-ahead, in addition to an intermediate carry generate circuit and a final group carry generate circuit. The output of earlier carry generate stages may be used as inputs to later stages. One type of carry generate circuit provides a “generate” output bit based on two data input bits and a “carry input” bit. A group carry generate circuit may be used to provide a group generate output for a particular stage based on a “propagate” input for that stage, a generate input for that stage, and a generate input for the previous stage. As another example, a final group carry circuit may be used to provide a “sum” output bit for a given bit position based on a propagate input for that bit position, a generate input for that bit position, a generate input for the previous bit position, and an exclusive-OR (XOR) input of the addends for the bit position. A person of skill in the art would appreciate that the generate input represents the results of an AND operation of the inputs a and b for that stage (i.e., ai AND bi) and that the propagate input represents the results of an OR operation of the inputs a and b for that stage (i.e., ai OR bi).
Carry generate circuits may be designed for use in cascaded differential domino circuits. A “domino circuit” is a type of circuit that is arranged in stages with the outputs from one stage (e.g., one gate) used as inputs into the next stage. The clock used with a domino circuit typically is delayed for each of the individual stages to provide a set-up time for the stages. The individual domino logic gates typically have one or more precharge blocks, which force the circuit to a known state during a precharge phase of a clock, and one or more evaluation blocks, which provide output values based on the input values during an evaluation phase of the clock. Domino circuits generally have a static stage in between the domino stages. For example, the domino circuit may have an inverter between the domino stages or a static complimentary metal-oxide semiconductor (CMOS) gate between the domino stages. By contrast, a cascaded domino circuit does not have any PMOS gates or transistors in the critical path of the logic. In a cascaded domino circuit, the outputs from one N-channel metal-oxide semiconductor (NMOS) domino gate (i.e., a gate with NMOS transistors in the evaluation block) may be directly connected to the inputs of another NMOS domino gate.
A “differential circuit” has complimentary sets of input and output terminals. The first set of input and output terminals may be referred to as the “true” inputs and outputs, and the second set may be referred to as the “compliment” inputs and outputs. For example, a differential adder circuit may have two true inputs “a” and “b” and may have a true output that outputs the result of an addition of a and b. This differential adder may also have two compliment inputs which receive the compliment values of that received by the corresponding true input (e.g., negative a and negative b) and a compliment output that outputs the compliment value of the true output (e.g., negative (a+b)).
Carry generate differential domino circuits may be difficult to design and manufacture because the true and compliment outputs of the circuit should begin to switch with the same edge rate and not be susceptible to pattern dependence and because the clock may arrive at the same time as the data or before the data. For these reasons, differential domino circuits such as cascaded differential domino carry generate circuits have not been widely used.